Rodriguez, Rennier and Gomez, Frederick Ray and Jr., Edwin Graycochea (2021) Augmented Sidewall Topology Simulation of Semiconductor Die. Journal of Engineering Research and Reports, 20 (6). pp. 70-74. ISSN 2582-2926
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433-Article Text-741-1-10-20221007.pdf - Published Version
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Official URL: https://doi.org/10.9734/jerr/2021/v20i617329
Abstract
The paper presents a modified design for wafer level semiconductor devices, using a CAD (computer-aided design) tool for visualization. The discussion provides a specialized manufacturing flow for the augmented die design through advanced wafer fabrication method and wafer cutting technique. Ultimately, the new package design would result for better visual inspection and interface anchoring between the device and the external board.
Item Type: | Article |
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Subjects: | South Asian Archive > Engineering |
Depositing User: | Unnamed user with email support@southasianarchive.com |
Date Deposited: | 03 Mar 2023 10:14 |
Last Modified: | 01 Jul 2024 13:20 |
URI: | http://article.journalrepositoryarticle.com/id/eprint/138 |